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x86/microcode/intel: Enable staging when available

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With staging support implemented, enable it when the CPU reports the
feature.

  [ bp: Sort in the MSR properly. ]

Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Chao Gao <chao.gao@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Tested-by: Anselm Busse <abusse@amazon.de>
Link: https://lore.kernel.org/20250320234104.8288-1-chang.seok.bae@intel.com
This commit is contained in:
Chang S. Bae
2025-09-21 15:48:41 -07:00
committed by Borislav Petkov (AMD)
parent 4ab410287b
commit bffeb2fd0b
2 changed files with 25 additions and 0 deletions
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8
arch/x86/include/asm/msr-index.h
View File

@@ -166,6 +166,10 @@
* Processor MMIO stale data
* vulnerabilities.
*/
#define ARCH_CAP_MCU_ENUM BIT(16) /*
* Indicates the presence of microcode update
* feature enumeration and status information.
*/
#define ARCH_CAP_FB_CLEAR BIT(17) /*
* VERW clears CPU fill buffer
* even on MDS_NO CPUs.
@@ -929,6 +933,10 @@
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
#define MSR_IA32_UCODE_WRITE 0x00000079
#define MSR_IA32_MCU_ENUMERATION 0x0000007b
#define MCU_STAGING BIT(4)
#define MSR_IA32_UCODE_REV 0x0000008b
/* Intel SGX Launch Enclave Public Key Hash MSRs */

17
arch/x86/kernel/cpu/microcode/intel.c
View File

@@ -983,6 +983,18 @@ static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c)
llc_size_per_core = (unsigned int)llc_size;
}
static __init bool staging_available(void)
{
u64 val;
val = x86_read_arch_cap_msr();
if (!(val & ARCH_CAP_MCU_ENUM))
return false;
rdmsrq(MSR_IA32_MCU_ENUMERATION, val);
return !!(val & MCU_STAGING);
}
struct microcode_ops * __init init_intel_microcode(void)
{
struct cpuinfo_x86 *c = &boot_cpu_data;
@@ -993,6 +1005,11 @@ struct microcode_ops * __init init_intel_microcode(void)
return NULL;
}
if (staging_available()) {
microcode_intel_ops.use_staging = true;
pr_info("Enabled staging feature.\n");
}
calc_llc_size_per_core(c);
return &microcode_intel_ops;