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74743c53a1
The clock controller of Loongson-2K0300 consists of three PLLs, requires an 120MHz external reference clock to function, and generates clocks in various frequencies for SoC peripherals. Clock definitions for previous SoC generations could be reused for most clock hardwares. There're two gates marked as critical, clk_node_gate and clk_boot_gate, which supply the CPU cores and the system configuration bus. Disabling them leads to a SoC hang. Signed-off-by: Yao Zi <ziyao@disroot.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
461 lines
16 KiB
C
461 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Author: Yinbo Zhu <zhuyinbo@loongson.cn>
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* Copyright (C) 2022-2023 Loongson Technology Corporation Limited
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <dt-bindings/clock/loongson,ls2k-clk.h>
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enum loongson2_clk_type {
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CLK_TYPE_PLL,
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CLK_TYPE_SCALE,
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CLK_TYPE_DIVIDER,
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CLK_TYPE_GATE,
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CLK_TYPE_FIXED,
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CLK_TYPE_NONE,
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};
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struct loongson2_clk_provider {
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void __iomem *base;
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struct device *dev;
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spinlock_t clk_lock; /* protect access to DIV registers */
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/* Must be last --ends in a flexible-array member. */
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struct clk_hw_onecell_data clk_data;
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};
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struct loongson2_clk_data {
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struct clk_hw hw;
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void __iomem *reg;
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u8 div_shift;
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u8 div_width;
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u8 mult_shift;
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u8 mult_width;
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u8 bit_idx;
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};
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struct loongson2_clk_board_info {
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u8 id;
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enum loongson2_clk_type type;
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const char *name;
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const char *parent_name;
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unsigned long fixed_rate;
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unsigned long flags;
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u8 reg_offset;
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u8 div_shift;
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u8 div_width;
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u8 mult_shift;
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u8 mult_width;
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u8 bit_idx;
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};
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#define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_DIVIDER, \
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.name = _name, \
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.parent_name = _pname, \
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.reg_offset = _offset, \
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.div_shift = _dshift, \
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.div_width = _dwidth, \
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}
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#define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \
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_dshift, _dwidth) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_PLL, \
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.name = _name, \
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.parent_name = NULL, \
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.reg_offset = _offset, \
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.mult_shift = _mshift, \
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.mult_width = _mwidth, \
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.div_shift = _dshift, \
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.div_width = _dwidth, \
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}
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#define CLK_SCALE(_id, _name, _pname, _offset, \
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_dshift, _dwidth) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_SCALE, \
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.name = _name, \
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.parent_name = _pname, \
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.reg_offset = _offset, \
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.div_shift = _dshift, \
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.div_width = _dwidth, \
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}
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#define CLK_SCALE_MODE(_id, _name, _pname, _offset, \
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_dshift, _dwidth, _midx) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_SCALE, \
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.name = _name, \
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.parent_name = _pname, \
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.reg_offset = _offset, \
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.div_shift = _dshift, \
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.div_width = _dwidth, \
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.bit_idx = _midx + 1, \
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}
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#define CLK_GATE(_id, _name, _pname, _offset, _bidx) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_GATE, \
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.name = _name, \
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.parent_name = _pname, \
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.reg_offset = _offset, \
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.bit_idx = _bidx, \
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}
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#define CLK_GATE_FLAGS(_id, _name, _pname, _offset, _bidx, \
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_flags) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_GATE, \
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.name = _name, \
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.parent_name = _pname, \
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.reg_offset = _offset, \
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.bit_idx = _bidx, \
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.flags = _flags \
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}
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#define CLK_FIXED(_id, _name, _pname, _rate) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_FIXED, \
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.name = _name, \
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.parent_name = _pname, \
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.fixed_rate = _rate, \
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}
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static const struct loongson2_clk_board_info ls2k0300_clks[] = {
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/* Reference Clock */
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CLK_PLL(LS2K0300_NODE_PLL, "pll_node", 0x00, 15, 9, 8, 7),
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CLK_PLL(LS2K0300_DDR_PLL, "pll_ddr", 0x08, 15, 9, 8, 7),
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CLK_PLL(LS2K0300_PIX_PLL, "pll_pix", 0x10, 15, 9, 8, 7),
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CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000),
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CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000),
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/* Node PLL */
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CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7),
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CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7),
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CLK_DIV(LS2K0300_CLK_I2S_DIV, "clk_i2s_div", "pll_node", 0x04, 8, 7),
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CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE, "clk_node_pll_gate", "clk_node_div", 0x00, 0),
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CLK_GATE(LS2K0300_CLK_GMAC_GATE, "clk_gmac_gate", "clk_gmac_div", 0x00, 1),
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CLK_GATE(LS2K0300_CLK_I2S_GATE, "clk_i2s_gate", "clk_i2s_div", 0x00, 2),
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CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate", "clk_node_scale", 0x24, 0,
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CLK_IS_CRITICAL),
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CLK_SCALE_MODE(LS2K0300_CLK_NODE_SCALE, "clk_node_scale", "clk_node_pll_gate", 0x20, 0, 3,
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3),
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/* DDR PLL */
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CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7),
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CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7),
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CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7),
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CLK_GATE(LS2K0300_CLK_NET_GATE, "clk_net_gate", "clk_net_div", 0x08, 1),
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CLK_GATE(LS2K0300_CLK_DEV_GATE, "clk_dev_gate", "clk_dev_div", 0x08, 2),
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CLK_GATE_FLAGS(LS2K0300_CLK_DDR_GATE, "clk_ddr_gate", "clk_ddr_div", 0x08, 0,
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CLK_IS_CRITICAL),
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/* PIX PLL */
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CLK_DIV(LS2K0300_CLK_PIX_DIV, "clk_pix_div", "pll_pix", 0x10, 24, 7),
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CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7),
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CLK_GATE(LS2K0300_CLK_PIX_PLL_GATE, "clk_pix_pll_gate", "clk_pix_div", 0x10, 0),
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CLK_GATE(LS2K0300_CLK_PIX_GATE, "clk_pix_gate", "clk_pix_scale", 0x24, 6),
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CLK_GATE(LS2K0300_CLK_GMACBP_GATE, "clk_gmacbp_gate", "clk_gmacbp_div", 0x10, 1),
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CLK_SCALE_MODE(LS2K0300_CLK_PIX_SCALE, "clk_pix_scale", "clk_pix_pll_gate", 0x20, 4, 3, 7),
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/* clk_dev_gate */
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CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, 24, 4),
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CLK_GATE(LS2K0300_CLK_USB_GATE, "clk_usb_gate", "clk_usb_scale", 0x24, 2),
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CLK_GATE(LS2K0300_CLK_SDIO_GATE, "clk_sdio_gate", "clk_sdio_scale", 0x24, 4),
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CLK_GATE(LS2K0300_CLK_APB_GATE, "clk_apb_gate", "clk_apb_scale", 0x24, 3),
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CLK_GATE_FLAGS(LS2K0300_CLK_BOOT_GATE, "clk_boot_gate", "clk_boot_scale", 0x24, 1,
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CLK_IS_CRITICAL),
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CLK_SCALE_MODE(LS2K0300_CLK_USB_SCALE, "clk_usb_scale", "clk_dev_gate", 0x20, 12, 3, 15),
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CLK_SCALE_MODE(LS2K0300_CLK_APB_SCALE, "clk_apb_scale", "clk_dev_gate", 0x20, 16, 3, 19),
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CLK_SCALE_MODE(LS2K0300_CLK_BOOT_SCALE, "clk_boot_scale", "clk_dev_gate", 0x20, 8, 3, 11),
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};
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static const struct loongson2_clk_board_info ls2k0500_clks[] = {
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CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
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CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6),
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CLK_PLL(LOONGSON2_DC_PLL, "pll_soc", 0x10, 16, 8, 8, 6),
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CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x18, 16, 8, 8, 6),
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CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x20, 16, 8, 8, 6),
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CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0, 24, 6),
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CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x8, 24, 6),
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CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0xc, 8, 6),
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CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_soc", 0x10, 24, 6),
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CLK_DIV(LOONGSON2_DC_CLK, "clk_sb", "pll_soc", 0x14, 0, 6),
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CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_soc", 0x14, 8, 6),
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CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x18, 24, 6),
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CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x20, 24, 6),
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CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", "clk_sb", 0x28, 8, 3),
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CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_sb", 0x28, 12, 3),
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CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_sb", 0x28, 16, 3),
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CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_sb", 0x28, 20, 3),
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{ /* Sentinel */ },
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};
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static const struct loongson2_clk_board_info ls2k1000_clks[] = {
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CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 32, 10, 26, 6),
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CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x10, 32, 10, 26, 6),
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CLK_PLL(LOONGSON2_DC_PLL, "pll_dc", 0x20, 32, 10, 26, 6),
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CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 32, 10, 26, 6),
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CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x40, 32, 10, 26, 6),
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CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0x8, 0, 6),
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CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x18, 0, 6),
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CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_ddr", 0x18, 22, 6),
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/*
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* The hda clk divisor in the upper 32bits and the clk-prodiver
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* layer code doesn't support 64bit io operation thus a conversion
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* is required that subtract shift by 32 and add 4byte to the hda
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* address
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*/
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CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0x22, 12, 7),
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CLK_DIV(LOONGSON2_DC_CLK, "clk_dc", "pll_dc", 0x28, 0, 6),
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CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_dc", 0x28, 22, 6),
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CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x38, 0, 6),
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CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x38, 0, 6),
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CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", NULL, 0x50, 8, 3),
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CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_gmac", 0x50, 12, 3),
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CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_gmac", 0x50, 16, 3),
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CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_gmac", 0x50, 20, 3),
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{ /* Sentinel */ },
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};
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static const struct loongson2_clk_board_info ls2k2000_clks[] = {
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CLK_PLL(LOONGSON2_DC_PLL, "pll_0", 0, 21, 9, 32, 6),
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CLK_PLL(LOONGSON2_DDR_PLL, "pll_1", 0x10, 21, 9, 32, 6),
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CLK_PLL(LOONGSON2_NODE_PLL, "pll_2", 0x20, 21, 9, 32, 6),
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CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 21, 9, 32, 6),
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CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x40, 21, 9, 32, 6),
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CLK_GATE(LOONGSON2_OUT0_GATE, "out0_gate", "pll_0", 0, 40),
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CLK_GATE(LOONGSON2_GMAC_GATE, "gmac_gate", "pll_0", 0, 41),
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CLK_GATE(LOONGSON2_RIO_GATE, "rio_gate", "pll_0", 0, 42),
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CLK_GATE(LOONGSON2_DC_GATE, "dc_gate", "pll_1", 0x10, 40),
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CLK_GATE(LOONGSON2_DDR_GATE, "ddr_gate", "pll_1", 0x10, 41),
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CLK_GATE(LOONGSON2_GPU_GATE, "gpu_gate", "pll_1", 0x10, 42),
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CLK_GATE(LOONGSON2_HDA_GATE, "hda_gate", "pll_2", 0x20, 40),
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CLK_GATE(LOONGSON2_NODE_GATE, "node_gate", "pll_2", 0x20, 41),
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CLK_GATE(LOONGSON2_EMMC_GATE, "emmc_gate", "pll_2", 0x20, 42),
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CLK_GATE(LOONGSON2_PIX0_GATE, "pix0_gate", "pll_pix0", 0x30, 40),
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CLK_GATE(LOONGSON2_PIX1_GATE, "pix1_gate", "pll_pix1", 0x40, 40),
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CLK_DIV(LOONGSON2_OUT0_CLK, "clk_out0", "out0_gate", 0, 0, 6),
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CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "gmac_gate", 0, 7, 6),
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CLK_DIV(LOONGSON2_RIO_CLK, "clk_rio", "rio_gate", 0, 14, 6),
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CLK_DIV(LOONGSON2_DC_CLK, "clk_dc", "dc_gate", 0x10, 0, 6),
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CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "gpu_gate", 0x10, 7, 6),
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CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "ddr_gate", 0x10, 14, 6),
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CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "hda_gate", 0x20, 0, 6),
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CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "node_gate", 0x20, 7, 6),
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CLK_DIV(LOONGSON2_EMMC_CLK, "clk_emmc", "emmc_gate", 0x20, 14, 6),
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CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x30, 0, 6),
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CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x40, 0, 6),
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CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_out0", 0x50, 12, 3),
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CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_out0", 0x50, 16, 3),
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CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_node", 0x50, 20, 3),
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CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", NULL, 0x50, 23, 3),
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CLK_SCALE(LOONGSON2_DES_CLK, "clk_des", "clk_node", 0x50, 40, 3),
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CLK_SCALE(LOONGSON2_I2S_CLK, "clk_i2s", "clk_node", 0x50, 44, 3),
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CLK_FIXED(LOONGSON2_MISC_CLK, "clk_misc", NULL, 50000000),
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{ /* Sentinel */ },
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};
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static inline struct loongson2_clk_data *to_loongson2_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct loongson2_clk_data, hw);
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}
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static inline unsigned long loongson2_rate_part(u64 val, u8 shift, u8 width)
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{
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return (val & GENMASK(shift + width - 1, shift)) >> shift;
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}
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static unsigned long loongson2_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u64 val, mult, div;
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struct loongson2_clk_data *clk = to_loongson2_clk(hw);
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val = readq(clk->reg);
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mult = loongson2_rate_part(val, clk->mult_shift, clk->mult_width);
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div = loongson2_rate_part(val, clk->div_shift, clk->div_width);
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return div_u64((u64)parent_rate * mult, div);
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}
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static const struct clk_ops loongson2_pll_recalc_ops = {
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.recalc_rate = loongson2_pll_recalc_rate,
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};
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static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u64 val, scale;
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u32 mode = 0;
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struct loongson2_clk_data *clk = to_loongson2_clk(hw);
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val = readq(clk->reg);
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scale = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
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if (clk->bit_idx)
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mode = val & BIT(clk->bit_idx - 1);
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return mode == 0 ? div_u64((u64)parent_rate * scale, 8) :
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div_u64((u64)parent_rate, scale);
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}
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static const struct clk_ops loongson2_freqscale_recalc_ops = {
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.recalc_rate = loongson2_freqscale_recalc_rate,
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};
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static struct clk_hw *loongson2_clk_register(const char *parent,
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struct loongson2_clk_provider *clp,
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const struct loongson2_clk_board_info *cld,
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const struct clk_ops *ops)
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{
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int ret;
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struct clk_hw *hw;
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struct loongson2_clk_data *clk;
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struct clk_init_data init = { };
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clk = devm_kzalloc(clp->dev, sizeof(*clk), GFP_KERNEL);
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if (!clk)
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return ERR_PTR(-ENOMEM);
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|
init.name = cld->name;
|
|
init.ops = ops;
|
|
init.flags = 0;
|
|
init.num_parents = 1;
|
|
init.parent_names = &parent;
|
|
|
|
clk->reg = clp->base + cld->reg_offset;
|
|
clk->div_shift = cld->div_shift;
|
|
clk->div_width = cld->div_width;
|
|
clk->mult_shift = cld->mult_shift;
|
|
clk->mult_width = cld->mult_width;
|
|
clk->bit_idx = cld->bit_idx;
|
|
clk->hw.init = &init;
|
|
|
|
hw = &clk->hw;
|
|
ret = devm_clk_hw_register(clp->dev, hw);
|
|
if (ret)
|
|
clk = ERR_PTR(ret);
|
|
|
|
return hw;
|
|
}
|
|
|
|
static int loongson2_clk_probe(struct platform_device *pdev)
|
|
{
|
|
int i, clks_num = 0;
|
|
struct clk_hw *hw;
|
|
struct device *dev = &pdev->dev;
|
|
struct loongson2_clk_provider *clp;
|
|
const struct loongson2_clk_board_info *p, *data;
|
|
const char *refclk_name, *parent_name;
|
|
|
|
data = device_get_match_data(dev);
|
|
if (!data)
|
|
return -EINVAL;
|
|
|
|
refclk_name = of_clk_get_parent_name(dev->of_node, 0);
|
|
if (IS_ERR(refclk_name))
|
|
return dev_err_probe(dev, PTR_ERR(refclk_name),
|
|
"failed to get refclk name\n");
|
|
|
|
for (p = data; p->name; p++)
|
|
clks_num = max(clks_num, p->id + 1);
|
|
|
|
clp = devm_kzalloc(dev, struct_size(clp, clk_data.hws, clks_num),
|
|
GFP_KERNEL);
|
|
if (!clp)
|
|
return -ENOMEM;
|
|
|
|
clp->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(clp->base))
|
|
return PTR_ERR(clp->base);
|
|
|
|
spin_lock_init(&clp->clk_lock);
|
|
clp->clk_data.num = clks_num;
|
|
clp->dev = dev;
|
|
|
|
/* Avoid returning NULL for unused id */
|
|
memset_p((void **)clp->clk_data.hws, ERR_PTR(-ENOENT), clks_num);
|
|
|
|
for (i = 0; i < clks_num; i++) {
|
|
p = &data[i];
|
|
parent_name = p->parent_name ? p->parent_name : refclk_name;
|
|
|
|
switch (p->type) {
|
|
case CLK_TYPE_PLL:
|
|
hw = loongson2_clk_register(parent_name, clp, p,
|
|
&loongson2_pll_recalc_ops);
|
|
break;
|
|
case CLK_TYPE_SCALE:
|
|
hw = loongson2_clk_register(parent_name, clp, p,
|
|
&loongson2_freqscale_recalc_ops);
|
|
break;
|
|
case CLK_TYPE_DIVIDER:
|
|
hw = devm_clk_hw_register_divider(dev, p->name,
|
|
parent_name, 0,
|
|
clp->base + p->reg_offset,
|
|
p->div_shift, p->div_width,
|
|
CLK_DIVIDER_ONE_BASED |
|
|
CLK_DIVIDER_ALLOW_ZERO,
|
|
&clp->clk_lock);
|
|
break;
|
|
case CLK_TYPE_GATE:
|
|
hw = devm_clk_hw_register_gate(dev, p->name, parent_name,
|
|
p->flags,
|
|
clp->base + p->reg_offset,
|
|
p->bit_idx, 0,
|
|
&clp->clk_lock);
|
|
break;
|
|
case CLK_TYPE_FIXED:
|
|
hw = devm_clk_hw_register_fixed_rate(dev, p->name, parent_name,
|
|
0, p->fixed_rate);
|
|
break;
|
|
default:
|
|
return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");
|
|
}
|
|
|
|
if (IS_ERR(hw))
|
|
return dev_err_probe(dev, PTR_ERR(hw),
|
|
"Register clk: %s, type: %u failed!\n",
|
|
p->name, p->type);
|
|
|
|
clp->clk_data.hws[p->id] = hw;
|
|
}
|
|
|
|
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clp->clk_data);
|
|
}
|
|
|
|
static const struct of_device_id loongson2_clk_match_table[] = {
|
|
{ .compatible = "loongson,ls2k0300-clk", .data = &ls2k0300_clks },
|
|
{ .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
|
|
{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
|
|
{ .compatible = "loongson,ls2k2000-clk", .data = &ls2k2000_clks },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, loongson2_clk_match_table);
|
|
|
|
static struct platform_driver loongson2_clk_driver = {
|
|
.probe = loongson2_clk_probe,
|
|
.driver = {
|
|
.name = "loongson2-clk",
|
|
.of_match_table = loongson2_clk_match_table,
|
|
},
|
|
};
|
|
module_platform_driver(loongson2_clk_driver);
|
|
|
|
MODULE_DESCRIPTION("Loongson2 clock driver");
|
|
MODULE_AUTHOR("Loongson Technology Corporation Limited");
|
|
MODULE_LICENSE("GPL");
|