Files
linux/drivers
Xing Zheng 20c389e656 clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-12 10:04:52 +02:00
..
2016-08-07 14:41:02 -06:00
2016-08-07 14:41:02 -06:00
2016-08-07 14:41:02 -06:00
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