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Felipe Balbi 248b122b13 usb: dwc3: core: fix cached revision on our structure

All our revision macros are defined with the entire
32-bits which we read from GSNPSID register, so we
must cache all 32-bits properly rather than masking
the top 16-bits.

This will fix all revision checks we have on current
driver.

Signed-off-by: Felipe Balbi <balbi@ti.com>

2011-12-14 21:59:30 +02:00

core.c

usb: dwc3: core: fix cached revision on our structure

2011-12-14 21:59:30 +02:00

core.h

usb: dwc3: gadget: allow clock gating to work

2011-10-04 10:25:56 -07:00

debug.h

2011-10-04 10:25:52 -07:00

debugfs.c

2011-10-04 10:25:52 -07:00

dwc3-omap.c