Files
linux/drivers
Gabe Black 2ec35fd503 clk: tegra: Fix PLLP rate table
This table had settings for 216MHz, but PLLP is (and is supposed to be)
configured at 408MHz.  If that table is used and PLLP_BASE_OVRRIDE is
not set, the kernel will panic in clk_pll_recalc_rate().

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17 16:18:02 +02:00
..
2014-02-17 16:18:02 +02:00
2014-02-14 10:40:47 +01:00
2014-01-15 14:51:22 -08:00
2014-02-13 11:12:00 -08:00