mirror of
https://github.com/torvalds/linux.git
synced 2026-02-04 15:28:49 +08:00
d5f1af7ece
A few differences needed by OCTEON: o These are DWC UARTS, but have USR at a different offset. o Internal SoC buses require reading back from registers to maintain write ordering. o 8250 on OCTEON appears with 64-bit wide registers, so when using readb/writeb in big endian mode we have to adjust the membase to hit the proper part of the register. o No UCV register, so we hard code some properties. Because OCTEON doesn't have a UCV register, I change where dw8250_setup_port(), which reads the UCV, is called by pushing it in to the OF and ACPI probe functions, and move unchanged dw8250_setup_port() earlier in the file. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: Jamie Iles <jamie@jamieiles.com> Cc: Jiri Slaby <jslaby@suse.cz> Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5516/ Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>