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7d7e7bce76
Add helper to read and write expansion registers without taking the mdio lock. Please note, that this changes the semantics of the read and write. Before there was no lock between selecting the expansion register and the actual read/write. This may lead to access failures if there are parallel accesses. Instead take the bus lock during the whole access cycle. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
82 lines
2.9 KiB
C
82 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*/
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#ifndef _LINUX_BCM_PHY_LIB_H
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#define _LINUX_BCM_PHY_LIB_H
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#include <linux/brcmphy.h>
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#include <linux/phy.h>
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/* 28nm only register definitions */
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#define MISC_ADDR(base, channel) base, channel
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#define DSP_TAP10 MISC_ADDR(0x0a, 0)
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#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
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#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
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#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
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#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
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#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
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#define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
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#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
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#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
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#define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
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#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
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#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
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int __bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
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int __bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
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int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
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int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
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static inline int bcm_phy_write_exp_sel(struct phy_device *phydev,
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u16 reg, u16 val)
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{
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return bcm_phy_write_exp(phydev, reg | MII_BCM54XX_EXP_SEL_ER, val);
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}
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int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val);
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int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum);
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int bcm_phy_write_misc(struct phy_device *phydev,
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u16 reg, u16 chl, u16 value);
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int bcm_phy_read_misc(struct phy_device *phydev,
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u16 reg, u16 chl);
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int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
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u16 val);
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int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow);
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int __bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val);
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int bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val);
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int __bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb);
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int bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb);
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int __bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask,
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u16 set);
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int bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask,
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u16 set);
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int bcm_phy_ack_intr(struct phy_device *phydev);
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int bcm_phy_config_intr(struct phy_device *phydev);
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int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down);
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int bcm_phy_set_eee(struct phy_device *phydev, bool enable);
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int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count);
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int bcm_phy_downshift_set(struct phy_device *phydev, u8 count);
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int bcm_phy_get_sset_count(struct phy_device *phydev);
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void bcm_phy_get_strings(struct phy_device *phydev, u8 *data);
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void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
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struct ethtool_stats *stats, u64 *data);
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void bcm_phy_r_rc_cal_reset(struct phy_device *phydev);
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int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev);
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int bcm_phy_enable_jumbo(struct phy_device *phydev);
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#endif /* _LINUX_BCM_PHY_LIB_H */
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