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riscv64: Add support for csrrc
This commit is contained in:
Petr Pavlu
committed by
Mark Wielaard
Mark Wielaard
parent
d18934dce3
commit
c5a916b655
@@ -14,7 +14,7 @@ The following ISA base and extensions are currently supported:
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| RV64A | Atomic | 22/22 | (2) |
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| RV64F | Single-precision floating-point | 30/30 | (3) |
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| RV64D | Double-precision floating-point | 32/32 | |
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| RV64Zicsr | Control & status register | 2/6 | (4), (5) |
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| RV64Zicsr | Control & status register | 3/6 | (4), (5) |
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| RV64Zifencei | Instruction-fetch fence | 0/1 | (6) |
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| RV64C | Compressed | 37/37 | |
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@@ -22,7 +22,7 @@ Notes:
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(1) MULHSU is not recognized.
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(2) LR and SC use the VEX "fallback" method which suffers from the ABA problem.
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(3) Operations do not check if the input operands are correctly NaN-boxed.
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(4) CSRRC, CSRRWI, CSRRSI and CSRRCI are not recognized.
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(4) CSRRWI, CSRRSI and CSRRCI are not recognized.
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(5) Only registers fflags, frm and fcsr are accepted.
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(6) FENCE.I is not recognized.
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@@ -3170,15 +3170,15 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
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{
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/* ------------ RV64Zicsr standard extension ------------- */
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/* --------------- csrr{w,s} rd, csr, rs1 ---------------- */
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/* -------------- csrr{w,s,c} rd, csr, rs1 --------------- */
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if (INSN(6, 0) == 0b1110011) {
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UInt rd = INSN(11, 7);
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UInt funct3 = INSN(14, 12);
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UInt rs1 = INSN(19, 15);
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UInt csr = INSN(31, 20);
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if ((funct3 != 0b001 && funct3 != 0b010) ||
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if ((funct3 != 0b001 && funct3 != 0b010 && funct3 != 0b011) ||
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(csr != 0x001 && csr != 0x002 && csr != 0x003)) {
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/* Invalid CSRR{W,S}, fall through. */
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/* Invalid CSRR{W,S,C}, fall through. */
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} else {
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switch (csr) {
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case 0x001: {
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@@ -3201,6 +3201,11 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
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expr = binop(Iop_Or32, mkexpr(fcsr),
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binop(Iop_And32, getIReg32(rs1), mkU32(0x1f)));
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break;
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case 0b011:
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expr = binop(Iop_And32, mkexpr(fcsr),
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unop(Iop_Not32, binop(Iop_And32, getIReg32(rs1),
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mkU32(0x1f))));
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break;
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default:
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vassert(0);
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}
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@@ -3232,6 +3237,14 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
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binop(Iop_And32, getIReg32(rs1), mkU32(0x7)),
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mkU8(5)));
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break;
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case 0b011:
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expr =
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binop(Iop_And32, mkexpr(fcsr),
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unop(Iop_Not32,
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binop(Iop_Shl32,
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binop(Iop_And32, getIReg32(rs1), mkU32(0x7)),
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mkU8(5))));
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break;
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default:
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vassert(0);
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}
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@@ -3254,6 +3267,11 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
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expr = binop(Iop_Or32, mkexpr(fcsr),
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binop(Iop_And32, getIReg32(rs1), mkU32(0xff)));
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break;
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case 0b011:
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expr = binop(Iop_And32, mkexpr(fcsr),
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unop(Iop_Not32, binop(Iop_And32, getIReg32(rs1),
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mkU32(0xff))));
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break;
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default:
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vassert(0);
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}
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@@ -3272,6 +3290,9 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
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case 0b010:
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name = "csrrs";
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break;
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case 0b011:
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name = "csrrc";
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break;
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default:
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vassert(0);
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}
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@@ -77,7 +77,38 @@ static void test_csr64_shared(void)
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TESTINST_1_1_CSR(4, "csrrs a0, fcsr, zero", 0xff, 0x00, a0, fcsr, zero);
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/* ----------------- csrrc rd, csr, rs1 ------------------ */
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/* Not currently handled. */
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/* fflags */
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TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0x00, 0x01, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0x00, 0x1f, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0xff, 0x1e, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0xff, 0x00, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0x00, 0xff, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc t5, fflags, t6", 0x00, 0x01, t5, fcsr, t6);
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TESTINST_1_1_CSR(4, "csrrc zero, fflags, a1", 0xff, 0x01, zero, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, fflags, zero", 0xff, 0x00, a0, fcsr, zero);
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/* frm */
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TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0x00, 0x1, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0x00, 0x7, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0xff, 0x6, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0xff, 0x0, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0x00, 0xff, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc t5, frm, t6", 0x00, 0x1, t5, fcsr, t6);
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TESTINST_1_1_CSR(4, "csrrc zero, frm, a1", 0xff, 0x1, zero, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, frm, zero", 0xff, 0x0, a0, fcsr, zero);
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/* fcsr */
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TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0x00, 0x01, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0x00, 0xff, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0xff, 0xfe, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0xff, 0x00, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0x00, 0xff, a0, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc t5, fcsr, t6", 0x00, 0x01, t5, fcsr, t6);
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TESTINST_1_1_CSR(4, "csrrc zero, fcsr, a1", 0xff, 0x01, zero, fcsr, a1);
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TESTINST_1_1_CSR(4, "csrrc a0, fcsr, zero", 0xff, 0x00, a0, fcsr, zero);
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/* -------------- csrrwi rd, csr, uimm[4:0] -------------- */
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/* Not currently handled. */
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@@ -143,3 +143,75 @@ csrrs zero, fcsr, a1 ::
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csrrs a0, fcsr, zero ::
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inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
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output: a0=0x00000000000000ff, fcsr=0x00000000000000ff
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csrrc a0, fflags, a1 ::
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inputs: a1=0x0000000000000001, fcsr=0x0000000000000000
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output: a0=0x0000000000000000, fcsr=0x0000000000000000
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csrrc a0, fflags, a1 ::
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inputs: a1=0x000000000000001f, fcsr=0x0000000000000000
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output: a0=0x0000000000000000, fcsr=0x0000000000000000
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csrrc a0, fflags, a1 ::
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inputs: a1=0x000000000000001e, fcsr=0x00000000000000ff
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output: a0=0x000000000000001f, fcsr=0x00000000000000e1
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csrrc a0, fflags, a1 ::
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inputs: a1=0x0000000000000000, fcsr=0x00000000000000ff
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output: a0=0x000000000000001f, fcsr=0x00000000000000ff
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csrrc a0, fflags, a1 ::
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inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
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output: a0=0x0000000000000000, fcsr=0x0000000000000000
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csrrc t5, fflags, t6 ::
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inputs: t6=0x0000000000000001, fcsr=0x0000000000000000
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output: t5=0x0000000000000000, fcsr=0x0000000000000000
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csrrc zero, fflags, a1 ::
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inputs: a1=0x0000000000000001, fcsr=0x00000000000000ff
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output: zero=0x0000000000000000, fcsr=0x00000000000000fe
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csrrc a0, fflags, zero ::
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inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
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output: a0=0x000000000000001f, fcsr=0x00000000000000ff
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csrrc a0, frm, a1 ::
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inputs: a1=0x0000000000000001, fcsr=0x0000000000000000
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output: a0=0x0000000000000000, fcsr=0x0000000000000000
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csrrc a0, frm, a1 ::
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inputs: a1=0x0000000000000007, fcsr=0x0000000000000000
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output: a0=0x0000000000000000, fcsr=0x0000000000000000
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csrrc a0, frm, a1 ::
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inputs: a1=0x0000000000000006, fcsr=0x00000000000000ff
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output: a0=0x0000000000000007, fcsr=0x000000000000003f
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csrrc a0, frm, a1 ::
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inputs: a1=0x0000000000000000, fcsr=0x00000000000000ff
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output: a0=0x0000000000000007, fcsr=0x00000000000000ff
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csrrc a0, frm, a1 ::
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inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
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output: a0=0x0000000000000000, fcsr=0x0000000000000000
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csrrc t5, frm, t6 ::
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inputs: t6=0x0000000000000001, fcsr=0x0000000000000000
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output: t5=0x0000000000000000, fcsr=0x0000000000000000
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csrrc zero, frm, a1 ::
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inputs: a1=0x0000000000000001, fcsr=0x00000000000000ff
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output: zero=0x0000000000000000, fcsr=0x00000000000000df
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csrrc a0, frm, zero ::
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inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
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output: a0=0x0000000000000007, fcsr=0x00000000000000ff
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csrrc a0, fcsr, a1 ::
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inputs: a1=0x0000000000000001, fcsr=0x0000000000000000
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output: a0=0x0000000000000000, fcsr=0x0000000000000000
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csrrc a0, fcsr, a1 ::
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inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
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output: a0=0x0000000000000000, fcsr=0x0000000000000000
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csrrc a0, fcsr, a1 ::
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inputs: a1=0x00000000000000fe, fcsr=0x00000000000000ff
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output: a0=0x00000000000000ff, fcsr=0x0000000000000001
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csrrc a0, fcsr, a1 ::
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inputs: a1=0x0000000000000000, fcsr=0x00000000000000ff
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output: a0=0x00000000000000ff, fcsr=0x00000000000000ff
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csrrc a0, fcsr, a1 ::
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inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
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output: a0=0x0000000000000000, fcsr=0x0000000000000000
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csrrc t5, fcsr, t6 ::
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inputs: t6=0x0000000000000001, fcsr=0x0000000000000000
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output: t5=0x0000000000000000, fcsr=0x0000000000000000
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csrrc zero, fcsr, a1 ::
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inputs: a1=0x0000000000000001, fcsr=0x00000000000000ff
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output: zero=0x0000000000000000, fcsr=0x00000000000000fe
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csrrc a0, fcsr, zero ::
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inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
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output: a0=0x00000000000000ff, fcsr=0x00000000000000ff
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