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46 lines
2.2 KiB
Plaintext
46 lines
2.2 KiB
Plaintext
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Status
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~~~~~~
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The RISC-V port targets the 64-bit RISC-V architecture and the Linux operating
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system. The port has been tested to work on real hardware and under QEMU.
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The following ISA base and extensions are currently supported:
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| Name | Description | #Instrs | Notes |
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| ------------ | --------------------------------- | ------- | -------- |
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| RV64I | Base instruction set | 52/52 | |
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| RV64M | Integer multiplication & division | 12/13 | (1) |
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| RV64A | Atomic | 22/22 | (2) |
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| RV64F | Single-precision floating-point | 30/30 | (3) |
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| RV64D | Double-precision floating-point | 32/32 | |
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| RV64Zicsr | Control & status register | 3/6 | (4), (5) |
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| RV64Zifencei | Instruction-fetch fence | 0/1 | (6) |
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| RV64C | Compressed | 37/37 | |
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Notes:
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(1) MULHSU is not recognized.
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(2) LR and SC use the VEX "fallback" method which suffers from the ABA problem.
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(3) Operations do not check if the input operands are correctly NaN-boxed.
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(4) CSRRWI, CSRRSI and CSRRCI are not recognized.
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(5) Only registers fflags, frm and fcsr are accepted.
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(6) FENCE.I is not recognized.
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Implementation tidying-up/TODO notes
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* Implement a proper "non-fallback" method for LR and SC instructions.
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* Add a check for correct NaN-boxing of 32-bit floating-point operands.
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* Optimize instruction selection, in particular make more use of <instr>i
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variants.
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* Optimize handling of floating-point exceptions. Avoid helpers and calculate
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exception flags using the same instruction which produced an actual result.
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* Review register usage by the codegen.
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* Avoid re-use of Intel-constants CFIC_IA_SPREL and CFIC_IA_BPREL. Generalize
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them for all architectures or introduce same CFIC_RISCV64_ variants.
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* Get rid of the typedef of vki_modify_ldt_t in include/vki/vki-riscv64-linux.h.
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* Review if setup_client_stack() should expose AT_SYSINFO_EHDR to clients.
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* Make sure that the final exit sequence in run_a_thread_NORETURN() is not racy
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in regards to accessing the thread state.
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