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drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency

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Clarify that the function is specific to PNV, making subsequent changes
slightly easier to grasp.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7d4e3c9a4220ff84af2741e5cd7bb62d1b4f2a44.1718356614.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2024-06-14 12:22:29 +03:00
parent 8b5a92ca24
commit 105dadedc4
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/i915/display/i9xx_wm.c
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@@ -70,7 +70,7 @@ static const struct cxsr_latency cxsr_latency_table[] = {
{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
};
static const struct cxsr_latency *intel_get_cxsr_latency(struct drm_i915_private *i915)
static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *i915)
{
int i;
@@ -637,7 +637,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
u32 reg;
unsigned int wm;
latency = intel_get_cxsr_latency(dev_priv);
latency = pnv_get_cxsr_latency(dev_priv);
if (!latency) {
drm_dbg_kms(&dev_priv->drm,
"Unknown FSB/MEM found, disable CxSR\n");
@@ -4029,7 +4029,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
g4x_setup_wm_latency(dev_priv);
dev_priv->display.funcs.wm = &g4x_wm_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
if (!intel_get_cxsr_latency(dev_priv)) {
if (!pnv_get_cxsr_latency(dev_priv)) {
drm_info(&dev_priv->drm,
"failed to find known CxSR latency "
"(found ddr%s fsb freq %d, mem freq %d), "