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HID: intel-thc-hid: intel-thc: Add THC interrupt handler
Add common interrupt handler to clear interrupt status and return interrupt type to caller for future handling. Co-developed-by: Even Xu <even.xu@intel.com> Signed-off-by: Even Xu <even.xu@intel.com> Signed-off-by: Xinpeng Sun <xinpeng.sun@intel.com> Tested-by: Rui Zhang <rui1.zhang@intel.com> Tested-by: Mark Pearson <mpearson-lenovo@squebb.ca> Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Mark Pearson <mpearson-lenovo@squebb.ca> Tested-by: Aaron Ma <aaron.ma@canonical.com> Signed-off-by: Jiri Kosina <jkosina@suse.com>
This commit is contained in:
@@ -802,6 +802,265 @@ void thc_ltr_unconfig(struct thc_device *dev)
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}
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EXPORT_SYMBOL_NS_GPL(thc_ltr_unconfig, "INTEL_THC");
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/**
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* thc_int_cause_read - Read interrupt cause register value
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*
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* @dev: The pointer of THC private device context
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*
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* Return: The interrupt cause register value
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*/
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u32 thc_int_cause_read(struct thc_device *dev)
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{
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u32 int_cause;
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regmap_read(dev->thc_regmap,
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THC_M_PRT_DEV_INT_CAUSE_REG_VAL_OFFSET, &int_cause);
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return int_cause;
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}
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EXPORT_SYMBOL_NS_GPL(thc_int_cause_read, "INTEL_THC");
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static void thc_print_txn_error_cause(const struct thc_device *dev)
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{
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bool known_error = false;
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u32 cause = 0;
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regmap_read(dev->thc_regmap, THC_M_PRT_ERR_CAUSE_OFFSET, &cause);
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if (cause & THC_M_PRT_ERR_CAUSE_PRD_ENTRY_ERR) {
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dev_err(dev->dev, "TXN Error: Invalid PRD Entry\n");
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known_error = true;
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}
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if (cause & THC_M_PRT_ERR_CAUSE_BUF_OVRRUN_ERR) {
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dev_err(dev->dev, "TXN Error: THC Buffer Overrun\n");
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known_error = true;
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}
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if (cause & THC_M_PRT_ERR_CAUSE_FRAME_BABBLE_ERR) {
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dev_err(dev->dev, "TXN Error: Frame Babble\n");
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known_error = true;
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}
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if (cause & THC_M_PRT_ERR_CAUSE_INVLD_DEV_ENTRY) {
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dev_err(dev->dev, "TXN Error: Invalid Device Register Setting\n");
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known_error = true;
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}
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/* Clear interrupt status bits */
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regmap_write(dev->thc_regmap, THC_M_PRT_ERR_CAUSE_OFFSET, cause);
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if (!known_error)
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dev_err(dev->dev, "TXN Error does not match any known value: 0x%X\n",
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cause);
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}
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/**
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* thc_interrupt_handler - Handle THC interrupts
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*
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* THC interrupts include several types: external touch device (TIC) non-DMA
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* interrupts, PIO completion interrupts, DMA interrtups, I2C subIP raw
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* interrupts and error interrupts.
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*
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* This is a help function for interrupt processing, it detects interrupt
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* type, clear the interrupt status bit and return the interrupt type to caller
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* for future processing.
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*
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* @dev: The pointer of THC private device context
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*
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* Return: The combined flag for interrupt type
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*/
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int thc_interrupt_handler(struct thc_device *dev)
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{
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u32 read_sts_1, read_sts_2, read_sts_sw, write_sts;
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u32 int_sts, err_cause, seq_cntrl, seq_sts;
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int interrupt_type = 0;
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regmap_read(dev->thc_regmap,
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THC_M_PRT_READ_DMA_INT_STS_1_OFFSET, &read_sts_1);
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if (read_sts_1 & THC_M_PRT_READ_DMA_INT_STS_NONDMA_INT_STS) {
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dev_dbg(dev->dev, "THC non-DMA device interrupt\n");
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regmap_write(dev->thc_regmap, THC_M_PRT_READ_DMA_INT_STS_1_OFFSET,
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NONDMA_INT_STS_BIT);
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interrupt_type |= BIT(THC_NONDMA_INT);
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return interrupt_type;
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}
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regmap_read(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET, &int_sts);
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if (int_sts & THC_M_PRT_INT_STATUS_TXN_ERR_INT_STS) {
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dev_err(dev->dev, "THC transaction error, int_sts: 0x%08X\n", int_sts);
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thc_print_txn_error_cause(dev);
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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TXN_ERR_INT_STS_BIT);
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interrupt_type |= BIT(THC_TXN_ERR_INT);
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return interrupt_type;
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}
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regmap_read(dev->thc_regmap, THC_M_PRT_ERR_CAUSE_OFFSET, &err_cause);
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regmap_read(dev->thc_regmap,
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THC_M_PRT_READ_DMA_INT_STS_2_OFFSET, &read_sts_2);
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if (err_cause & THC_M_PRT_ERR_CAUSE_BUF_OVRRUN_ERR ||
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read_sts_1 & THC_M_PRT_READ_DMA_INT_STS_STALL_STS ||
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read_sts_2 & THC_M_PRT_READ_DMA_INT_STS_STALL_STS) {
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dev_err(dev->dev, "Buffer overrun or RxDMA engine stalled!\n");
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thc_print_txn_error_cause(dev);
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regmap_write(dev->thc_regmap, THC_M_PRT_READ_DMA_INT_STS_2_OFFSET,
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THC_M_PRT_READ_DMA_INT_STS_STALL_STS);
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regmap_write(dev->thc_regmap, THC_M_PRT_READ_DMA_INT_STS_1_OFFSET,
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THC_M_PRT_READ_DMA_INT_STS_STALL_STS);
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regmap_write(dev->thc_regmap, THC_M_PRT_ERR_CAUSE_OFFSET,
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THC_M_PRT_ERR_CAUSE_BUF_OVRRUN_ERR);
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interrupt_type |= BIT(THC_TXN_ERR_INT);
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return interrupt_type;
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}
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if (int_sts & THC_M_PRT_INT_STATUS_FATAL_ERR_INT_STS) {
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dev_err_once(dev->dev, "THC FATAL error, int_sts: 0x%08X\n", int_sts);
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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TXN_FATAL_INT_STS_BIT);
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interrupt_type |= BIT(THC_FATAL_ERR_INT);
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return interrupt_type;
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}
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regmap_read(dev->thc_regmap,
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THC_M_PRT_SW_SEQ_CNTRL_OFFSET, &seq_cntrl);
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regmap_read(dev->thc_regmap,
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THC_M_PRT_SW_SEQ_STS_OFFSET, &seq_sts);
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if (seq_cntrl & THC_M_PRT_SW_SEQ_CNTRL_THC_SS_CD_IE &&
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seq_sts & THC_M_PRT_SW_SEQ_STS_TSSDONE) {
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dev_dbg(dev->dev, "THC_SS_CD_IE and TSSDONE are set\n");
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interrupt_type |= BIT(THC_PIO_DONE_INT);
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}
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if (read_sts_1 & THC_M_PRT_READ_DMA_INT_STS_EOF_INT_STS) {
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dev_dbg(dev->dev, "Got RxDMA1 Read Interrupt\n");
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regmap_write(dev->thc_regmap,
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THC_M_PRT_READ_DMA_INT_STS_1_OFFSET, read_sts_1);
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interrupt_type |= BIT(THC_RXDMA1_INT);
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}
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if (read_sts_2 & THC_M_PRT_READ_DMA_INT_STS_EOF_INT_STS) {
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dev_dbg(dev->dev, "Got RxDMA2 Read Interrupt\n");
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regmap_write(dev->thc_regmap,
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THC_M_PRT_READ_DMA_INT_STS_2_OFFSET, read_sts_2);
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interrupt_type |= BIT(THC_RXDMA2_INT);
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}
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regmap_read(dev->thc_regmap,
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THC_M_PRT_READ_DMA_INT_STS_SW_OFFSET, &read_sts_sw);
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if (read_sts_sw & THC_M_PRT_READ_DMA_INT_STS_DMACPL_STS) {
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dev_dbg(dev->dev, "Got SwDMA Read Interrupt\n");
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regmap_write(dev->thc_regmap,
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THC_M_PRT_READ_DMA_INT_STS_SW_OFFSET, read_sts_sw);
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dev->swdma_done = true;
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wake_up_interruptible(&dev->swdma_complete_wait);
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interrupt_type |= BIT(THC_SWDMA_INT);
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}
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regmap_read(dev->thc_regmap,
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THC_M_PRT_WRITE_INT_STS_OFFSET, &write_sts);
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if (write_sts & THC_M_PRT_WRITE_INT_STS_THC_WRDMA_CMPL_STATUS) {
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dev_dbg(dev->dev, "Got TxDMA Write complete Interrupt\n");
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regmap_write(dev->thc_regmap,
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THC_M_PRT_WRITE_INT_STS_OFFSET, write_sts);
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dev->write_done = true;
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wake_up_interruptible(&dev->write_complete_wait);
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interrupt_type |= BIT(THC_TXDMA_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_DEV_RAW_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_DEV_RAW_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_UNDER_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_UNDER_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_OVER_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_OVER_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_FULL_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_FULL_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_OVER_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_OVER_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_EMPTY_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_EMPTY_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_ABRT_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_ABRT_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_ACTIVITY_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_ACTIVITY_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_SCL_STUCK_AT_LOW_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_SCL_STUCK_AT_LOW_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_STOP_DET_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_STOP_DET_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_START_DET_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_START_DET_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (int_sts & THC_M_PRT_INT_STATUS_THC_I2C_IC_MST_ON_HOLD_INT_STS) {
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regmap_write(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET,
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THC_M_PRT_INT_STATUS_THC_I2C_IC_MST_ON_HOLD_INT_STS);
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interrupt_type |= BIT(THC_I2CSUBIP_INT);
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}
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if (!interrupt_type)
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interrupt_type |= BIT(THC_UNKNOWN_INT);
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return interrupt_type;
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}
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EXPORT_SYMBOL_NS_GPL(thc_interrupt_handler, "INTEL_THC");
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MODULE_AUTHOR("Xinpeng Sun <xinpeng.sun@intel.com>");
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MODULE_AUTHOR("Even Xu <even.xu@intel.com>");
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@@ -23,6 +23,31 @@ enum thc_port_type {
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THC_PORT_TYPE_I2C = 1,
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};
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/**
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* THC interrupt flag
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* @THC_NONDMA_INT: THC non-DMA interrupt
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* @THC_RXDMA1_INT: THC RxDMA1 interrupt
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* @THC_RXDMA2_INT: THC RxDMA2 interrupt
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* @THC_SWDMA_INT: THC SWDMA interrupt
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* @THC_TXDMA_INT: THC TXDMA interrupt
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* @THC_PIO_DONE_INT: THC PIO complete interrupt
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* @THC_I2CSUBIP_INT: THC I2C subsystem interrupt
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* @THC_TXN_ERR_INT: THC transfer error interrupt
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* @THC_FATAL_ERR_INT: THC fatal error interrupt
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*/
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enum thc_int_type {
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THC_NONDMA_INT = 0,
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THC_RXDMA1_INT = 1,
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THC_RXDMA2_INT = 2,
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THC_SWDMA_INT = 3,
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THC_TXDMA_INT = 4,
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THC_PIO_DONE_INT = 5,
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THC_I2CSUBIP_INT = 6,
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THC_TXN_ERR_INT = 7,
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THC_FATAL_ERR_INT = 8,
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THC_UNKNOWN_INT
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};
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/**
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* struct thc_device - THC private device struct
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* @thc_regmap: MMIO regmap structure for accessing THC registers
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@@ -71,5 +96,7 @@ int thc_interrupt_quiesce(const struct thc_device *dev, bool int_quiesce);
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void thc_ltr_config(struct thc_device *dev, u32 active_ltr_us, u32 lp_ltr_us);
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void thc_change_ltr_mode(struct thc_device *dev, u32 ltr_mode);
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void thc_ltr_unconfig(struct thc_device *dev);
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u32 thc_int_cause_read(struct thc_device *dev);
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int thc_interrupt_handler(struct thc_device *dev);
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#endif /* _INTEL_THC_DEV_H_ */
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