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LoongArch: Add unaligned access support
Loongson-2 series (Loongson-2K500, Loongson-2K1000) don't support unaligned access in hardware, while Loongson-3 series (Loongson-3A5000, Loongson-3C5000) are configurable whether support unaligned access in hardware. This patch add unaligned access emulation for those LoongArch processors without hardware support. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Huacai Chen
@@ -433,8 +433,8 @@ ignore-unaligned-usertrap
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On architectures where unaligned accesses cause traps, and where this
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feature is supported (``CONFIG_SYSCTL_ARCH_UNALIGN_NO_WARN``;
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currently, ``arc`` and ``ia64``), controls whether all unaligned traps
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are logged.
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currently, ``arc``, ``ia64`` and ``loongarch``), controls whether all
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unaligned traps are logged.
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= =============================================================
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0 Log all unaligned accesses.
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@@ -1457,8 +1457,8 @@ unaligned-trap
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On architectures where unaligned accesses cause traps, and where this
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feature is supported (``CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW``; currently,
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``arc`` and ``parisc``), controls whether unaligned traps are caught
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and emulated (instead of failing).
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``arc``, ``parisc`` and ``loongarch``), controls whether unaligned traps
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are caught and emulated (instead of failing).
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= ========================================================
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0 Do not emulate unaligned accesses.
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@@ -121,6 +121,8 @@ config LOONGARCH
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select RTC_LIB
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select SMP
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select SPARSE_IRQ
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select SYSCTL_ARCH_UNALIGN_ALLOW
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select SYSCTL_ARCH_UNALIGN_NO_WARN
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select SYSCTL_EXCEPTION_TRACE
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select SWIOTLB
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select TRACE_IRQFLAGS_SUPPORT
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@@ -76,6 +76,10 @@ enum reg2i12_op {
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ldbu_op = 0xa8,
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ldhu_op = 0xa9,
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ldwu_op = 0xaa,
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flds_op = 0xac,
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fsts_op = 0xad,
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fldd_op = 0xae,
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fstd_op = 0xaf,
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};
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enum reg2i14_op {
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@@ -146,6 +150,10 @@ enum reg3_op {
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ldxbu_op = 0x7040,
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ldxhu_op = 0x7048,
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ldxwu_op = 0x7050,
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fldxs_op = 0x7060,
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fldxd_op = 0x7068,
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fstxs_op = 0x7070,
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fstxd_op = 0x7078,
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amswapw_op = 0x70c0,
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amswapd_op = 0x70c1,
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amaddw_op = 0x70c2,
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@@ -566,4 +574,10 @@ static inline void emit_##NAME(union loongarch_instruction *insn, \
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DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op)
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struct pt_regs;
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void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc);
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unsigned long unaligned_read(void __user *addr, void *value, unsigned long n, bool sign);
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unsigned long unaligned_write(void __user *addr, unsigned long value, unsigned long n);
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#endif /* _ASM_INST_H */
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@@ -38,7 +38,7 @@ struct thread_info {
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#define INIT_THREAD_INFO(tsk) \
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{ \
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.task = &tsk, \
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.flags = 0, \
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.flags = _TIF_FIXADE, \
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.cpu = 0, \
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.preempt_count = INIT_PREEMPT_COUNT, \
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}
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@@ -7,7 +7,8 @@ extra-y := vmlinux.lds
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obj-y += head.o cpu-probe.o cacheinfo.o env.o setup.o entry.o genex.o \
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traps.o irq.o idle.o process.o dma.o mem.o io.o reset.o switch.o \
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elf.o syscall.o signal.o time.o topology.o inst.o ptrace.o vdso.o
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elf.o syscall.o signal.o time.o topology.o inst.o ptrace.o vdso.o \
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unaligned.o
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obj-$(CONFIG_ACPI) += acpi.o
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obj-$(CONFIG_EFI) += efi.o
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@@ -368,13 +368,40 @@ asmlinkage void noinstr do_ade(struct pt_regs *regs)
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irqentry_exit(regs, state);
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}
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/* sysctl hooks */
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int unaligned_enabled __read_mostly = 1; /* Enabled by default */
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int no_unaligned_warning __read_mostly = 1; /* Only 1 warning by default */
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asmlinkage void noinstr do_ale(struct pt_regs *regs)
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{
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unsigned int *pc;
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irqentry_state_t state = irqentry_enter(regs);
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perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr);
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/*
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* Did we catch a fault trying to load an instruction?
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*/
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if (regs->csr_badvaddr == regs->csr_era)
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goto sigbus;
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if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
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goto sigbus;
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if (!unaligned_enabled)
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goto sigbus;
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if (!no_unaligned_warning)
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show_registers(regs);
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pc = (unsigned int *)exception_era(regs);
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emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc);
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goto out;
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sigbus:
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die_if_kernel("Kernel ale access", regs);
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force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
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out:
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irqentry_exit(regs, state);
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}
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499
arch/loongarch/kernel/unaligned.c
Normal file
499
arch/loongarch/kernel/unaligned.c
Normal file
@@ -0,0 +1,499 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Handle unaligned accesses by emulation.
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) 2014 Imagination Technologies Ltd.
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*/
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/debugfs.h>
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#include <linux/perf_event.h>
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#include <asm/asm.h>
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#include <asm/branch.h>
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#include <asm/fpu.h>
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#include <asm/inst.h>
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#include "access-helper.h"
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#ifdef CONFIG_DEBUG_FS
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static u32 unaligned_instructions_user;
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static u32 unaligned_instructions_kernel;
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#endif
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static inline unsigned long read_fpr(unsigned int idx)
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{
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#define READ_FPR(idx, __value) \
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__asm__ __volatile__("movfr2gr.d %0, $f"#idx"\n\t" : "=r"(__value));
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unsigned long __value;
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switch (idx) {
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case 0:
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READ_FPR(0, __value);
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break;
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case 1:
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READ_FPR(1, __value);
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break;
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case 2:
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READ_FPR(2, __value);
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break;
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case 3:
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READ_FPR(3, __value);
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break;
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case 4:
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READ_FPR(4, __value);
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break;
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case 5:
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READ_FPR(5, __value);
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break;
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case 6:
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READ_FPR(6, __value);
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break;
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case 7:
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READ_FPR(7, __value);
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break;
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case 8:
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READ_FPR(8, __value);
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break;
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case 9:
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READ_FPR(9, __value);
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break;
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case 10:
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READ_FPR(10, __value);
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break;
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case 11:
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READ_FPR(11, __value);
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break;
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case 12:
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READ_FPR(12, __value);
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break;
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case 13:
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READ_FPR(13, __value);
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break;
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case 14:
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READ_FPR(14, __value);
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break;
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case 15:
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READ_FPR(15, __value);
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break;
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case 16:
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READ_FPR(16, __value);
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break;
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case 17:
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READ_FPR(17, __value);
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break;
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case 18:
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READ_FPR(18, __value);
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break;
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case 19:
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READ_FPR(19, __value);
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break;
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case 20:
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READ_FPR(20, __value);
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break;
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case 21:
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READ_FPR(21, __value);
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break;
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case 22:
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READ_FPR(22, __value);
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break;
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case 23:
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READ_FPR(23, __value);
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break;
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case 24:
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READ_FPR(24, __value);
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break;
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case 25:
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READ_FPR(25, __value);
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break;
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case 26:
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READ_FPR(26, __value);
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break;
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case 27:
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READ_FPR(27, __value);
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break;
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case 28:
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READ_FPR(28, __value);
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break;
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case 29:
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READ_FPR(29, __value);
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break;
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case 30:
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READ_FPR(30, __value);
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break;
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case 31:
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READ_FPR(31, __value);
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break;
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default:
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panic("unexpected idx '%d'", idx);
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}
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#undef READ_FPR
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return __value;
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}
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static inline void write_fpr(unsigned int idx, unsigned long value)
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{
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#define WRITE_FPR(idx, value) \
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__asm__ __volatile__("movgr2fr.d $f"#idx", %0\n\t" :: "r"(value));
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switch (idx) {
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case 0:
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WRITE_FPR(0, value);
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break;
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case 1:
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WRITE_FPR(1, value);
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break;
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case 2:
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WRITE_FPR(2, value);
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break;
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case 3:
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WRITE_FPR(3, value);
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break;
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case 4:
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WRITE_FPR(4, value);
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break;
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case 5:
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WRITE_FPR(5, value);
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break;
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case 6:
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WRITE_FPR(6, value);
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break;
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case 7:
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WRITE_FPR(7, value);
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break;
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case 8:
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WRITE_FPR(8, value);
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break;
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case 9:
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WRITE_FPR(9, value);
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break;
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case 10:
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WRITE_FPR(10, value);
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break;
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case 11:
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WRITE_FPR(11, value);
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break;
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case 12:
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WRITE_FPR(12, value);
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break;
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case 13:
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WRITE_FPR(13, value);
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break;
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case 14:
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WRITE_FPR(14, value);
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break;
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case 15:
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WRITE_FPR(15, value);
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break;
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case 16:
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WRITE_FPR(16, value);
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break;
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case 17:
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WRITE_FPR(17, value);
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break;
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case 18:
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WRITE_FPR(18, value);
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break;
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case 19:
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WRITE_FPR(19, value);
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break;
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case 20:
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WRITE_FPR(20, value);
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break;
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case 21:
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WRITE_FPR(21, value);
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break;
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case 22:
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WRITE_FPR(22, value);
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break;
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case 23:
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WRITE_FPR(23, value);
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break;
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case 24:
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WRITE_FPR(24, value);
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break;
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case 25:
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WRITE_FPR(25, value);
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break;
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case 26:
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WRITE_FPR(26, value);
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break;
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case 27:
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WRITE_FPR(27, value);
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break;
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case 28:
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WRITE_FPR(28, value);
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break;
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case 29:
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WRITE_FPR(29, value);
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break;
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case 30:
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WRITE_FPR(30, value);
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break;
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case 31:
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WRITE_FPR(31, value);
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break;
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default:
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panic("unexpected idx '%d'", idx);
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}
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#undef WRITE_FPR
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}
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void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc)
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{
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bool fp = false;
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bool sign, write;
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bool user = user_mode(regs);
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unsigned int res, size = 0;
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unsigned long value = 0;
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union loongarch_instruction insn;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
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__get_inst(&insn.word, pc, user);
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switch (insn.reg2i12_format.opcode) {
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case ldh_op:
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size = 2;
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sign = true;
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write = false;
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break;
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case ldhu_op:
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size = 2;
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sign = false;
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write = false;
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break;
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case sth_op:
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size = 2;
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sign = true;
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write = true;
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break;
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case ldw_op:
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size = 4;
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sign = true;
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write = false;
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break;
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case ldwu_op:
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size = 4;
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sign = false;
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write = false;
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break;
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case stw_op:
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size = 4;
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sign = true;
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write = true;
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break;
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case ldd_op:
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size = 8;
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sign = true;
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write = false;
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break;
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case std_op:
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size = 8;
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sign = true;
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write = true;
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break;
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case flds_op:
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size = 4;
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fp = true;
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sign = true;
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write = false;
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break;
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case fsts_op:
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size = 4;
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fp = true;
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sign = true;
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write = true;
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break;
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case fldd_op:
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size = 8;
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fp = true;
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sign = true;
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write = false;
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break;
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case fstd_op:
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size = 8;
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fp = true;
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sign = true;
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write = true;
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break;
|
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}
|
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|
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switch (insn.reg2i14_format.opcode) {
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case ldptrw_op:
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size = 4;
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sign = true;
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write = false;
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break;
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case stptrw_op:
|
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size = 4;
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sign = true;
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write = true;
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break;
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case ldptrd_op:
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size = 8;
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sign = true;
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write = false;
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break;
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case stptrd_op:
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size = 8;
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sign = true;
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write = true;
|
||||
break;
|
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}
|
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|
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switch (insn.reg3_format.opcode) {
|
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case ldxh_op:
|
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size = 2;
|
||||
sign = true;
|
||||
write = false;
|
||||
break;
|
||||
case ldxhu_op:
|
||||
size = 2;
|
||||
sign = false;
|
||||
write = false;
|
||||
break;
|
||||
case stxh_op:
|
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size = 2;
|
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sign = true;
|
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write = true;
|
||||
break;
|
||||
case ldxw_op:
|
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size = 4;
|
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sign = true;
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write = false;
|
||||
break;
|
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case ldxwu_op:
|
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size = 4;
|
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sign = false;
|
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write = false;
|
||||
break;
|
||||
case stxw_op:
|
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size = 4;
|
||||
sign = true;
|
||||
write = true;
|
||||
break;
|
||||
case ldxd_op:
|
||||
size = 8;
|
||||
sign = true;
|
||||
write = false;
|
||||
break;
|
||||
case stxd_op:
|
||||
size = 8;
|
||||
sign = true;
|
||||
write = true;
|
||||
break;
|
||||
case fldxs_op:
|
||||
size = 4;
|
||||
fp = true;
|
||||
sign = true;
|
||||
write = false;
|
||||
break;
|
||||
case fstxs_op:
|
||||
size = 4;
|
||||
fp = true;
|
||||
sign = true;
|
||||
write = true;
|
||||
break;
|
||||
case fldxd_op:
|
||||
size = 8;
|
||||
fp = true;
|
||||
sign = true;
|
||||
write = false;
|
||||
break;
|
||||
case fstxd_op:
|
||||
size = 8;
|
||||
fp = true;
|
||||
sign = true;
|
||||
write = true;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!size)
|
||||
goto sigbus;
|
||||
if (user && !access_ok(addr, size))
|
||||
goto sigbus;
|
||||
|
||||
if (!write) {
|
||||
res = unaligned_read(addr, &value, size, sign);
|
||||
if (res)
|
||||
goto fault;
|
||||
|
||||
/* Rd is the same field in any formats */
|
||||
if (!fp)
|
||||
regs->regs[insn.reg3_format.rd] = value;
|
||||
else {
|
||||
if (is_fpu_owner())
|
||||
write_fpr(insn.reg3_format.rd, value);
|
||||
else
|
||||
set_fpr64(¤t->thread.fpu.fpr[insn.reg3_format.rd], 0, value);
|
||||
}
|
||||
} else {
|
||||
/* Rd is the same field in any formats */
|
||||
if (!fp)
|
||||
value = regs->regs[insn.reg3_format.rd];
|
||||
else {
|
||||
if (is_fpu_owner())
|
||||
value = read_fpr(insn.reg3_format.rd);
|
||||
else
|
||||
value = get_fpr64(¤t->thread.fpu.fpr[insn.reg3_format.rd], 0);
|
||||
}
|
||||
|
||||
res = unaligned_write(addr, value, size);
|
||||
if (res)
|
||||
goto fault;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
if (user)
|
||||
unaligned_instructions_user++;
|
||||
else
|
||||
unaligned_instructions_kernel++;
|
||||
#endif
|
||||
|
||||
compute_return_era(regs);
|
||||
|
||||
return;
|
||||
|
||||
fault:
|
||||
/* Did we have an exception handler installed? */
|
||||
if (fixup_exception(regs))
|
||||
return;
|
||||
|
||||
die_if_kernel("Unhandled kernel unaligned access", regs);
|
||||
force_sig(SIGSEGV);
|
||||
|
||||
return;
|
||||
|
||||
sigbus:
|
||||
die_if_kernel("Unhandled kernel unaligned access", regs);
|
||||
force_sig(SIGBUS);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
static int __init debugfs_unaligned(void)
|
||||
{
|
||||
struct dentry *d;
|
||||
|
||||
d = debugfs_create_dir("loongarch", NULL);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
|
||||
debugfs_create_u32("unaligned_instructions_user",
|
||||
S_IRUGO, d, &unaligned_instructions_user);
|
||||
debugfs_create_u32("unaligned_instructions_kernel",
|
||||
S_IRUGO, d, &unaligned_instructions_kernel);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(debugfs_unaligned);
|
||||
#endif
|
||||
@@ -3,4 +3,4 @@
|
||||
# Makefile for LoongArch-specific library files.
|
||||
#
|
||||
|
||||
lib-y += delay.o clear_user.o copy_user.o dump_tlb.o
|
||||
lib-y += delay.o clear_user.o copy_user.o dump_tlb.o unaligned.o
|
||||
|
||||
84
arch/loongarch/lib/unaligned.S
Normal file
84
arch/loongarch/lib/unaligned.S
Normal file
@@ -0,0 +1,84 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/asmmacro.h>
|
||||
#include <asm/asm-extable.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/export.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
.L_fixup_handle_unaligned:
|
||||
li.w a0, -EFAULT
|
||||
jr ra
|
||||
|
||||
/*
|
||||
* unsigned long unaligned_read(void *addr, void *value, unsigned long n, bool sign)
|
||||
*
|
||||
* a0: addr
|
||||
* a1: value
|
||||
* a2: n
|
||||
* a3: sign
|
||||
*/
|
||||
SYM_FUNC_START(unaligned_read)
|
||||
beqz a2, 5f
|
||||
|
||||
li.w t2, 0
|
||||
addi.d t0, a2, -1
|
||||
slli.d t1, t0, 3
|
||||
add.d a0, a0, t0
|
||||
|
||||
beqz a3, 2f
|
||||
1: ld.b t3, a0, 0
|
||||
b 3f
|
||||
|
||||
2: ld.bu t3, a0, 0
|
||||
3: sll.d t3, t3, t1
|
||||
or t2, t2, t3
|
||||
addi.d t1, t1, -8
|
||||
addi.d a0, a0, -1
|
||||
addi.d a2, a2, -1
|
||||
bgtz a2, 2b
|
||||
4: st.d t2, a1, 0
|
||||
|
||||
move a0, a2
|
||||
jr ra
|
||||
|
||||
5: li.w a0, -EFAULT
|
||||
jr ra
|
||||
|
||||
_asm_extable 1b, .L_fixup_handle_unaligned
|
||||
_asm_extable 2b, .L_fixup_handle_unaligned
|
||||
_asm_extable 4b, .L_fixup_handle_unaligned
|
||||
SYM_FUNC_END(unaligned_read)
|
||||
|
||||
/*
|
||||
* unsigned long unaligned_write(void *addr, unsigned long value, unsigned long n)
|
||||
*
|
||||
* a0: addr
|
||||
* a1: value
|
||||
* a2: n
|
||||
*/
|
||||
SYM_FUNC_START(unaligned_write)
|
||||
beqz a2, 3f
|
||||
|
||||
li.w t0, 0
|
||||
1: srl.d t1, a1, t0
|
||||
2: st.b t1, a0, 0
|
||||
addi.d t0, t0, 8
|
||||
addi.d a2, a2, -1
|
||||
addi.d a0, a0, 1
|
||||
bgtz a2, 1b
|
||||
|
||||
move a0, a2
|
||||
jr ra
|
||||
|
||||
3: li.w a0, -EFAULT
|
||||
jr ra
|
||||
|
||||
_asm_extable 2b, .L_fixup_handle_unaligned
|
||||
SYM_FUNC_END(unaligned_write)
|
||||
Reference in New Issue
Block a user