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riscv: ptrace: Optimize the allocation of vector regset

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The vector regset uses the maximum possible vlen value to estimate the
.n field. But not all the hardwares support the maximum vlen. Linux
might wastes time to prepare a large memory buffer(about 2^6 pages) for
the vector regset.

The regset can only copy vector registers when the process are using
vector. Add .active callback and determine the n field of vector regset
in riscv_v_setup_ctx_cache() doesn't affect the ptrace syscall and
coredump. It can avoid oversized allocations and better matches real
hardware limits.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Andy Chiu <andybnac@gmail.com>
Tested-by: Andy Chiu <andybnac@gmail.com>
Link: https://patch.msgid.link/20251013091318.467864-2-yongxuan.wang@sifive.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Yong-Xuan Wang
2025-11-17 21:19:29 -07:00
committed by Paul Walmsley
parent 3ac022bf38
commit 6efb1a9462
3 changed files with 24 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/riscv/include/asm/vector.h
View File

@@ -51,6 +51,7 @@ void put_cpu_vector_context(void);
void riscv_v_thread_free(struct task_struct *tsk);
void __init riscv_v_setup_ctx_cache(void);
void riscv_v_thread_alloc(struct task_struct *tsk);
void __init update_regset_vector_info(unsigned long size);
static inline u32 riscv_v_flags(void)
{

24
arch/riscv/kernel/ptrace.c
View File

@@ -153,6 +153,17 @@ static int riscv_vr_set(struct task_struct *target,
0, riscv_v_vsize);
return ret;
}
static int riscv_vr_active(struct task_struct *target, const struct user_regset *regset)
{
if (!(has_vector() || has_xtheadvector()))
return -ENODEV;
if (!riscv_v_vstate_query(task_pt_regs(target)))
return 0;
return regset->n;
}
#endif
#ifdef CONFIG_RISCV_ISA_SUPM
@@ -184,7 +195,7 @@ static int tagged_addr_ctrl_set(struct task_struct *target,
}
#endif
static const struct user_regset riscv_user_regset[] = {
static struct user_regset riscv_user_regset[] __ro_after_init = {
[REGSET_X] = {
USER_REGSET_NOTE_TYPE(PRSTATUS),
.n = ELF_NGREG,
@@ -207,11 +218,10 @@ static const struct user_regset riscv_user_regset[] = {
[REGSET_V] = {
USER_REGSET_NOTE_TYPE(RISCV_VECTOR),
.align = 16,
.n = ((32 * RISCV_MAX_VLENB) +
sizeof(struct __riscv_v_regset_state)) / sizeof(__u32),
.size = sizeof(__u32),
.regset_get = riscv_vr_get,
.set = riscv_vr_set,
.active = riscv_vr_active,
},
#endif
#ifdef CONFIG_RISCV_ISA_SUPM
@@ -233,6 +243,14 @@ static const struct user_regset_view riscv_user_native_view = {
.n = ARRAY_SIZE(riscv_user_regset),
};
#ifdef CONFIG_RISCV_ISA_V
void __init update_regset_vector_info(unsigned long size)
{
riscv_user_regset[REGSET_V].n = (size + sizeof(struct __riscv_v_regset_state)) /
sizeof(__u32);
}
#endif
struct pt_regs_offset {
const char *name;
int offset;

2
arch/riscv/kernel/vector.c
View File

@@ -66,6 +66,8 @@ void __init riscv_v_setup_ctx_cache(void)
if (!(has_vector() || has_xtheadvector()))
return;
update_regset_vector_info(riscv_v_vsize);
riscv_v_user_cachep = kmem_cache_create_usercopy("riscv_vector_ctx",
riscv_v_vsize, 16, SLAB_PANIC,
0, riscv_v_vsize, NULL);