The current implementation gets device lifetime tracking wrong. The
problem is that allocation of struct counter_device is controlled by the
individual drivers but this structure contains a struct device that
might have to live longer than a driver is bound. As a result a command
sequence like:
{ sleep 5; echo bang; } > /dev/counter0 &
sleep 1;
echo 40000000.timer:counter > /sys/bus/platform/drivers/stm32-timer-counter/unbind
can keep a reference to the struct device and unbinding results in
freeing the memory occupied by this device resulting in an oops.
This commit provides two new functions (plus some helpers):
- counter_alloc() to allocate a struct counter_device that is
automatically freed once the embedded struct device is released
- counter_add() to register such a device.
Note that this commit doesn't fix any issues, all drivers have to be
converted to these new functions to correct the lifetime problems.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20211230150300.72196-14-u.kleine-koenig@pengutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
When firmware load failed, kernel report task hung as follows:
INFO: task xrun:5191 blocked for more than 147 seconds.
Tainted: G W 5.16.0-rc5-next-20211220+ #11
"echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
task:xrun state:D stack: 0 pid: 5191 ppid: 270 flags:0x00000004
Call Trace:
__schedule+0xc12/0x4b50 kernel/sched/core.c:4986
schedule+0xd7/0x260 kernel/sched/core.c:6369 (discriminator 1)
schedule_timeout+0x7aa/0xa80 kernel/time/timer.c:1857
wait_for_completion+0x181/0x290 kernel/sched/completion.c:85
lattice_ecp3_remove+0x32/0x40 drivers/misc/lattice-ecp3-config.c:221
spi_remove+0x72/0xb0 drivers/spi/spi.c:409
lattice_ecp3_remove() wait for signals from firmware loading, but when
load failed, firmware_load() does not send this signal. This cause
device remove hung. Fix it by sending signal even if load failed.
Fixes: 781551df57 ("misc: Add Lattice ECP3 FPGA configuration via SPI")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Link: https://lore.kernel.org/r/20211228125522.3122284-1-weiyongjun1@huawei.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Vinod writes:
phy-for-5.17
- New support:
- Qualcomm eDP PHY driver
- Qualcomm SM8450 UFS, USB2, USB3, PCIe0 and PCIe1 phy support
- Lan966x ethernet serdes PHY driver
- Support for uniphier NXI & Pro4 SoC
- Qualcomm SM6350 USB2 support
- Amlogic Meson8 HDMI TX PHY driver
- Rockchip rk3568 usb2 support
- Intel Thunder Bay eMMC PHY driver
- Freescale IMX8 PCIe phy driver
- Updates:
- Cadence Sierra driver updates for multilink configurations
- Bcm usb2 updates for Phy reg space
* tag 'phy-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits)
phy: cadence: Sierra: Add support for derived reference clock output
dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock
phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
phy: cadence: Sierra: Add support for PHY multilink configurations
phy: cadence: Sierra: Fix to get correct parent for mux clocks
phy: cadence: Sierra: Update single link PCIe register configuration
phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation
phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
phy: cadence: Sierra: Add PHY PCS common register configurations
phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation
phy: cadence: Sierra: Add support to get SSC type from device tree
dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names
phy: cadence: Sierra: Prepare driver to add support for multilink configurations
phy: cadence: Sierra: Use of_device_get_match_data() to get driver data
phy: mediatek: Fix missing check in mtk_mipi_tx_probe
phy: uniphier-usb3ss: fix unintended writing zeros to PHY register
phy: phy-mtk-tphy: use new io helpers to access register
phy: phy-mtk-xsphy: use new io helpers to access register
phy: mediatek: add helpers to update bits of registers
...
Vinod writes:
soundwire updates for 5.17-rc1
- Remove redundant version number read in qcom driver
* tag 'soundwire-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire:
soundwire: qcom: remove redundant version number read
Jonathan writes:
2nd set of new device support etc for IIO in the 5.17 cycle.
A small additional set of things that just missed the previous
pull request and have mostly been through plenty of review before the
holiday period began (or are trivial). I've not taken some other series
on the list to allow for more eyes after the holiday period.
New device support
* adi,admv1013
- New driver for this wideband microwave upconverter including dt-bindings
and some device specific ABI due to the need to describe phase calibrations
of a differential channel on both i and q phases. Previously we could
do differential or i/q but not both on the same channel. The driver
ABI uses a workaround for core support which will do until we know if
this is a common requirement for which a more generic solution is
needed.
MAINTAINERS:
* Add Haibo Chen as a maintainer for various NXP SoC ADCs.
Minor cleanup:
* sunrise_co2
- Make sure an uninitialized value isn't used to set *val in read_raw().
Not a real bug, but a compiler or reviewer can't tell that based
on what they can see locally.
* tag 'iio-for-5.17b' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio:
iio: chemical: sunrise_co2: set val parameter only on success
dt-bindings:iio:adc: update the maintainer of vf610-adc
MAINTAINERS: add imx7d/imx6sx/imx6ul/imx8qxp and vf610 adc maintainer
Documentation:ABI:testing:admv1013: add ABI docs
dt-bindings: iio: frequency: add admv1013 doc
iio: frequency: admv1013: add support for ADMV1013
There are currently 2 ways to create a set of sysfs files for a
kobj_type, through the default_attrs field, and the default_groups
field. Move the UIO code to use default_groups field which has been the
preferred way since aa30f47cf6 ("kobject: Add support for default
attribute groups to kobj_type") so that we can soon get rid of the
obsolete default_attrs field.
Link: https://lore.kernel.org/r/20211228131319.249324-1-gregkh@linuxfoundation.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Clang static analysis reports this representative warning
sunrise_co2.c:410:9: warning: Assigned value is garbage or undefined
*val = value;
^ ~~~~~
The ealier call to sunrise_read_word can fail without setting
value. So defer setting val until we know the read was successful.
Fixes: c397894e24 ("iio: chemical: Add Senseair Sunrise 006-0-007 driver")
Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20211224150833.3278236-1-trix@redhat.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Sierra has derived differential reference clock output which is sourced
after the spread spectrum generation has been added. Add support to drive
derived reference clock out of serdes. Model this derived clock as a
"clock" so that platforms using this can enable it.
Sierra Main LC VCO PLL divider 1 clock is programmed to output 100MHz
clock output.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-16-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add register sequences for PCIe + QSGMII PHY multilink configuration.
PHY configuration for multi-link operation is done in two steps.
e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII
other 2 lanes. Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this
case, PLLLC is used for PCIe and PLLLC1 is used for QSGMII.
PHY is configured in two steps as described below.
[1] For first step, the register values are selected as
[TYPE_PCIE][TYPE_QSGMII][ssc].
This will configure PHY registers associated for PCIe involving PLLLC
registers and registers for first 2 lanes of PHY.
[2] In second step, the register values are selected as
[TYPE_QSGMII][TYPE_PCIE][ssc].
This will configure PHY registers associated for QSGMII involving
PLLLC1 registers and registers for other 2 lanes of PHY.
This completes the PHY configuration for multilink operation.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-14-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Fix get_parent() callback to return the correct index of the parent for
PLL_CMNLC1 clock. Add a separate table of register values corresponding
to the parent index for PLL_CMNLC1. Update set_parent() callback
accordingly.
Fixes: 28081b7285 ("phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)")
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-12-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Oded writes:
This tag contains habanalabs driver changes for v5.17:
- Support reset-during-reset. In case the f/w notifies the driver
that the f/w is going to reset the device, the driver should
support that even if it is in the middle of doing another
reset
- Support events from f/w that arrive during device resets.
These events would be ignored which is bad as critical errors
would not be reported and treated by the driver.
- Don't kill processes that hold the control device open during
hard-reset of the device. The control device operations can't
crash if done during hard-reset. And usually, only monitoring
applications are using the control device, so killing them
defies their purpose.
- Fix handling of hwmon nodes when working with legacy f/w
- Change the compute context pointer to be boolean. This pointer
was abused by multiple code paths that wanted fast access to
the compute context structure.
- Add uapi to fetch historical errors. This is necessary as errors
sometimes result in hard-reset where the user application is
being terminated.
- Optimize GAUDI's MMU cache invalidation.
- Add support for loading the latest f/w.
- Add uapi to fetch HBM replacement and pending rows information.
- Multiple bug fixes to the reset code.
- Multiple bug fixes for Multi-CS ioctl code.
- Multiple bug fixes for wait-for-interrupt ioctl code.
- Many small bug fixes and cleanups.
* tag 'misc-habanalabs-next-2021-12-27' of https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux: (70 commits)
habanalabs: support hard-reset scheduling during soft-reset
habanalabs: add a lock to protect multiple reset variables
habanalabs: refactor reset information variables
habanalabs: handle skip multi-CS if handling not done
habanalabs: add CPU-CP packet for engine core ASID cfg
habanalabs: replace some -ENOTTY with -EINVAL
habanalabs: fix comments according to kernel-doc
habanalabs: fix endianness when reading cpld version
habanalabs: change wait_for_interrupt implementation
habanalabs: prevent wait if CS in multi-CS list completed
habanalabs: modify cpu boot status error print
habanalabs: clean MMU headers definitions
habanalabs: expose soft reset sysfs nodes for inference ASIC
habanalabs: sysfs support for two infineon versions
habanalabs: keep control device alive during hard reset
habanalabs: fix hwmon handling for legacy f/w
habanalabs: add current PI value to cpu packets
habanalabs: remove in_debug check in device open
habanalabs: return correct clock throttling period
habanalabs: wait again for multi-CS if no CS completed
...
