Martin Leung 5ec43eda85 drm/amd/display: enabling seamless boot sequence for dcn2 ...

[Why]
Seamless boot (building SW state inheriting BIOS-initialized timing) was
enabled on DCN2, including fixes

[How]
Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
Pixel clock.

This is part 2 of 2 for seamless boot NV10

Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2019-08-15 10:54:27 -05:00

..

drm

drm/amd/display: enabling seamless boot sequence for dcn2

2019-08-15 10:54:27 -05:00

host1x

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ipu-v3

Merge tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm

2019-07-15 19:04:27 -07:00

vga

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Makefile

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