Files
linux/drivers/gpu/drm
Martin Leung 5ec43eda85 drm/amd/display: enabling seamless boot sequence for dcn2
[Why]
Seamless boot (building SW state inheriting BIOS-initialized timing) was
enabled on DCN2, including fixes

[How]
Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
Pixel clock.

This is part 2 of 2 for seamless boot NV10

Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15 10:54:27 -05:00
..
2019-08-02 17:31:39 +01:00
2019-07-22 21:24:10 +02:00
2019-08-06 08:21:53 +02:00
2019-08-06 09:20:58 +02:00
2019-07-22 21:24:10 +02:00
2019-07-15 18:11:30 +02:00
2019-07-22 21:24:10 +02:00
2019-07-17 12:52:55 +02:00
2019-06-25 00:10:24 +02:00
2019-07-17 12:47:57 +02:00
2019-06-30 09:48:05 +02:00
2019-07-15 18:11:30 +02:00
2019-07-22 21:24:10 +02:00
2019-07-17 12:52:55 +02:00
2019-07-15 18:11:31 +02:00
2019-07-17 12:52:55 +02:00
2019-07-22 21:24:10 +02:00
2019-07-15 18:11:30 +02:00
2019-07-17 12:52:55 +02:00
2019-07-17 12:52:20 +02:00
2019-07-22 21:24:10 +02:00
2019-07-25 17:35:20 +02:00
2019-07-15 18:11:30 +02:00
2019-07-15 18:11:30 +02:00
2019-07-22 21:24:10 +02:00
2019-07-22 21:24:10 +02:00
2019-07-22 21:24:10 +02:00
2019-07-22 21:24:10 +02:00
2019-07-25 10:45:07 +02:00
2019-07-31 15:17:03 +02:00