Zhao Qiang e9501b975a clk: qoriq: modify MAX_PLL_DIV to 32
On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 19:48:09 -07:00
2020-08-14 19:56:56 -07:00
2020-08-16 13:04:57 -07:00

Linux kernel
============

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